Module: ppl/ppl Branch: master Commit: 2f490ee5d25afea0c21e16463e27059223c734d0 URL: http://www.cs.unipr.it/git/gitweb.cgi?p=ppl/ppl.git;a=commit;h=2f490ee5d25af...

Author: Enea Zaffanella zaffanella@cs.unipr.it Date: Wed Feb 15 15:43:49 2012 +0100

Make comparison against zero explicit. Detected by ECLAIR service utypflag.

---

src/Float.inlines.hh | 12 ++++++------ src/Rounding_Dir.inlines.hh | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/Float.inlines.hh b/src/Float.inlines.hh index 88bb1a1..fb2b78d 100644 --- a/src/Float.inlines.hh +++ b/src/Float.inlines.hh @@ -60,7 +60,7 @@ float_ieee754_half::negate() {

inline bool float_ieee754_half::sign_bit() const { - return !!(word & SGN_MASK); + return (word & SGN_MASK) != 0; }

inline void @@ -121,7 +121,7 @@ float_ieee754_single::negate() {

inline bool float_ieee754_single::sign_bit() const { - return !!(word & SGN_MASK); + return (word & SGN_MASK) != 0; }

inline void @@ -187,7 +187,7 @@ float_ieee754_double::negate() {

inline bool float_ieee754_double::sign_bit() const { - return !!(msp & MSP_SGN_MASK); + return (msp & MSP_SGN_MASK) != 0; }

inline void @@ -268,7 +268,7 @@ float_ibm_single::negate() {

inline bool float_ibm_single::sign_bit() const { - return !!(word & SGN_MASK); + return (word & SGN_MASK) != 0; }

inline void @@ -336,7 +336,7 @@ float_intel_double_extended::negate() {

inline bool float_intel_double_extended::sign_bit() const { - return !!(msp & MSP_SGN_MASK); + return (msp & MSP_SGN_MASK) != 0; }

inline void @@ -416,7 +416,7 @@ float_ieee754_quad::negate() {

inline bool float_ieee754_quad::sign_bit() const { - return !!(msp & MSP_SGN_MASK); + return (msp & MSP_SGN_MASK) != 0; }

inline void diff --git a/src/Rounding_Dir.inlines.hh b/src/Rounding_Dir.inlines.hh index 8a4b281..af2de1c 100644 --- a/src/Rounding_Dir.inlines.hh +++ b/src/Rounding_Dir.inlines.hh @@ -70,7 +70,7 @@ round_inverse(Rounding_Dir dir) {

inline bool round_strict_relation(Rounding_Dir dir) { - return dir & ROUND_STRICT_RELATION; + return (dir & ROUND_STRICT_RELATION) != 0; }

#if PPL_CAN_CONTROL_FPU