Module: ppl/ppl Branch: master Commit: 4d9ca69f6866d37bae028ecf45421daa380446d1 URL: http://www.cs.unipr.it/git/gitweb.cgi?p=ppl/ppl.git;a=commit;h=4d9ca69f6866d...

Author: Abramo Bagnara abramo.bagnara@gmail.com Date: Sat Mar 28 15:41:29 2009 +0100

These efficiency related FIXME's are not scheduled for 0.10.1

---

src/checked.inlines.hh | 12 +++++------- 1 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/checked.inlines.hh b/src/checked.inlines.hh index 7ef3072..b340bd9 100644 --- a/src/checked.inlines.hh +++ b/src/checked.inlines.hh @@ -512,11 +512,10 @@ inline typename Enable_If<(!Safe_Conversion<T1, T2>::value eq(const T1& x, const T2& y) { PPL_DIRTY_TEMP(T1, tmp); Result r = assign_r(tmp, y, static_cast<Rounding_Dir>(ROUND_DIRECT | ROUND_FPU_CHECK_INEXACT)); - // FIXME(0.10.1): Can we do any better? - // We can do this also without fpu inexact check using - // a conversion back and forth and then testing equality. - // We should code this in checked_float.inlines.hh, probably - // it's faster also if fpu supports inexact check. + // FIXME: We can do this also without fpu inexact check using a + // conversion back and forth and then testing equality. We should + // code this in checked_float.inlines.hh, probably it's faster also + // if fpu supports inexact check. assert(r != V_LE && r != V_GE && r != V_LGE); return r == V_EQ && x == tmp; } @@ -563,8 +562,7 @@ le(const T1& x, const T2& y) { case V_LE: case V_GE: case V_LGE: - // FIXME(0.10.1): Can we do any better? - // See comment above. + // FIXME: See comment above. assert(0); default: return false;